1. Field of the Invention
The present invention generally relates to a method and a system for hot spot identification, inspection, and review, and more particularly to a method and a SORIL e-beam tool that can provide high resolution scanning, and large scanning field of view to quickly identify, inspect, and review hot spots on a specimen for semiconductor manufacturing process.
2. Description of the Prior Art
The semiconductor fabrication includes combinations of thermal oxidation process, doping process, lithographic process, etching process, deposition process, chemical mechanical polishing processes, and other processes. The combination of these processes can form integrated circuits in a small chip, and applications of the semiconductor devices can be the computation, communication, storage, and other specific applications.
Every single step must be kept at a very high yield such that hundreds of steps involved in the semiconductor fabrication can be commercial profitable. For examples, if averaged yield among a hundred processes is 99%, and the end result to a product would only have 36.6% yield. However, if averaged yield is enhanced to 99.9%, the final product will have approximately 90.5% yield, which would enhance volume profit in commercial consideration. Hence, yield management is very crucial.
A killer, in the semiconductor manufacture process, is the defect which will result in the malfunction of a chip. That means there may be some defects that will not affect function of circuits. Hence, from the original design, killers are the crucial target to be eliminated in every semiconductor fabrication process.
However, for nowadays semiconductor fabrication process, such as the node has reached below 20 nm, killers are hard to be found. Thus, another strategy to maintain yield needs to be developed. A hot spot is a weak point which has higher possibility to incur killers during design or process fabrication. Thus, to monitor and identify all hot spots in semiconductor process will be a critical step to enhance yield rate.
One method for identifying hot spot is by using conjectures and experiences with original design layout data, such as GDS (Graphic Design System) information, to develop algorithms and failure bit map, but this method can't predict so well for the new developed mask and process. Moreover, such conjectures and experiences will highly depend on manufacturing process; even if there are different processes with the same mask, hot spots may always be variant. Further, also by using software and algorithm, this method is a very time consuming process, such as several month for a hot spot to be conjectured.
Another method is by using optical inspection tool, but resolution for an optical inspection tool is too large to inspect hot spots smaller than 20 nm, due to wavelength of the optical source is 193 nm. Even by using algorithm to conjecture unusual areas in an optical inspection, not only resolution of optical inspection tool can be hardly used for features less than 20 nm but also small defects in the scanned image are averaged out by using algorithm. Further, foundry now concerns defect of half pitch of the semiconductor node; that is features about 10 nm or below must be detected.
Therefore, a new method and system to identify and review hot spots for the next semiconductor node is necessary.